The technical field of this invention is solid state integrated circuit fabrication and, more particularly, methods for fabricating voltage programmable link structures.
Programmable conductive paths, particularly "links" between two or more distinct metallization layers, are increasingly employed in solid-state integrated circuit fabrication to produce a wide variety of programmable circuits including, for example, programmable read only memories ("PROMs"), and other programmable electronic devices.
Most typically, such devices are "programmed" by the application of an electrical voltage to trigger an "antifuse" link structure disposed between two metallization layers and thereby establish an electrical connection across a region of the device which had previously been an insulator.
While this approach should in theory permit an almost limitless variety of custom circuits, certain factors make programmable devices difficult to implement. Some antifuse link structures rely upon crude melting mechanisms that require the dedication of large surface areas on the wafer to insure an electrical connection is formed.
In addition, there is an inherent tension between the desire for a link structure that will remain insulative at normal operating voltages for the solid state device (e.g., nominally five volts), and the desire that a conductive path can be reliably formed on each and every occasion by the application of a higher programming voltage (e.g., about ten volts).
If a link structure breaks down at a voltage below the "programming" or activation voltage, an unintended altered circuit will result, thereby disturbing the normal operation of the existing circuit. On the other hand, if the programmable link is over-resistant to the programming voltage, either the conductive path will not be formed when desired or greater voltages must be applied with the attendant risk of damage to nearby structures on the wafer.
Various programmable link structures have been proposed as alternatives to the crude structures which merely rely on melting or fusion processes. For example, the use of vertical holes ("vias") filled with amorphous silicon or doped silicon compositions have been disclosed in U.S. Pat. No. 4,847,732 issued to Stopper et al. and in European Patent Application Pub. No. 416,903 by Whitten et al. In this approach, a programming voltage of about 10 volts or more is used to locally heat the amorphous silicon, and thereby convert it into a conductive polycrystalline structure.
Unfortunately, amorphous silicon-based and polysilicon-based link structures have a number of disadvantages, including the limited conductivity of polysilicon, the potential presence of leakage currents through the amorphous materials even prior to activation which can lead to inadvertent breakdown, and the need for large area structures to maximize the conductivity after the link has been activated.
Another approach which has been proposed is the use of composite or sandwich structures of silicon oxide-silicon nitride-silicon oxide as the link material. When such a sandwich composite is deposited in a via, contacting a first (lower) conductive layer and then covered by a second (upper) conductive layer, it can be rendered conductive by application of a programming voltage (e.g., a pulse of about 18 volts at a current of about 1.0 mA for a time duration of about 100 msec).
A typical sandwich structure of this type is disclosed in U.S. Pat. No. 4,823,181 in which a bottom oxide layer of about 2-5 nanometers, a central silicon nitride layer of 4-10 nanometers, and a top oxide layer of 0-5 nanometers are described. Although this sandwich structure is relatively easy to fabricate (because the lower oxide layer can be thermally grown when the underlying conductor is polysilicon), these link devices also suffer a number of shortcomings in use.
The oxide-nitride-oxide compositions are poorly compatible with aluminum due to chemical reactivity and thermal effects. Aluminum readily reacts with silicon dioxide over time to form aluminum oxide and aluminum silicon complexes which can degrade the integrity of the link structure. Additionally, during wafer processing, sintering and other heating processes cause aluminum to expand more rapidly than the link composition, which applies thermal stress to the insulative oxide component of the link and can result in microfractures which facilitate premature breakdown. For these reasons, prior art sandwich link structures typically are used to form vertical conductive paths only between different layers of polysilicon lines. Polysilicon is typically a less desirable choice for conductive lines because its electrical resistance is about three orders of magnitude higher than most metals, causing signals to slow down and/or limiting the number of links that can be used in a given cell or chip.
Moreover, due to the thinness of the sandwich structures described in U.S. Pat. No. 4,823,181, they are particularly sensitive to the problems of reliability and consistency in usage. Thin oxide-nitride-oxide sandwich structures are prone to premature breakdown, while thicker structures can require high voltages (i.e. over 15 volts) with significant deviation in the actual breakdown voltage necessary from one link to another. Such high programming voltages can trigger parasitic responses and reactions in field devices and, hence, should be avoided.
There exists a need for more reliable programmable link structures, particularly structures which are voltage programmable at a nominal voltage of about ten volts, while providing stable insulation without breakdown at the normal operating voltage of about 5.0 volts.